The present invention relates generally to an improved data processing system, and more specifically, to flushing pending cache misses in a multithread data processing system.
Conventional data processing systems and microprocessor systems incorporate simultaneous multithreading techniques to improve utilization of computing resources and computer performance. These data processing systems can experience a cache miss at a cache hierarchy level (e.g., L1, L2, L3, L4 . . . LN). The cache misses can cause a thread corresponding to a given cache miss to saturate and over-consume the majority of the computing resources.